Nvidia Rubin GPU: 2026 launch specs, supply-chain signals, and Rubin Ultra roadmap

Nvidia's Rubin GPU is the first generation after Blackwell, launching in late 2026 with a new architecture, HBM4 memory, and a packaging step to CoWoS-L. It is the first Nvidia data-center GPU to be designed from the ground up for inference at hyperscaler scale rather than training-first. This article covers the leaked specs, supply-chain signals from TSMC and SK Hynix, the Rubin Ultra follow-up, and what it means for AMD MI400, Google TPU v7, and the broader 2026-2027 AI-infrastructure cycle.

What is Nvidia Rubin?

Rubin is the codename for Nvidia's sixth-generation data-center GPU architecture, succeeding Blackwell (which itself shipped in late 2024 and powers H100/B200 systems). It was first disclosed at GTC 2025 by Jensen Huang as a "next-generation" platform, with full architectural details trickling out via supply-chain leaks through 2026.

Three things make Rubin different from Blackwell:

1. HBM4 memory — the first GPU generation to use HBM4, doubling per-stack bandwidth vs HBM3e.
2. CoWoS-L packaging — Nvidia's transition from CoWoS-S to CoWoS-L allows larger interposer sizes (~120×120mm), needed for Rubin Ultra's 2027 chiplet design.
3. Inference-first design — Rubin increases INT8/FP8 throughput per watt more aggressively than FP16/BF16, reflecting the post-training inference-economics shift.

Confirmed and leaked specs

Spec	Hopper (H100)	Blackwell (B200)	Rubin (R100)	Rubin Ultra (RU100)
Process	TSMC 4N	TSMC 4NP	TSMC N3P (3nm)	TSMC N3P + chiplet
Memory	HBM3 (80GB)	HBM3e (192GB)	HBM4 (288GB)	HBM4e (1TB)
Memory bandwidth	3.35 TB/s	8 TB/s	13 TB/s	32 TB/s
FP4 TOPS	3,958 (Hopper+FP8)	18,000	30,000+	100,000+
TDP	700W	1000W (B200)	~1200W	~2400W (chiplet)
Launch	2022	2024	Q4 2026	H2 2027

Specs are leaks, not official Nvidia disclosures. Nvidia has confirmed HBM4 use and the TSMC 3nm node for Rubin but not exact TOPS or memory configurations.

Supply-chain signals

Three supply-chain signals make Rubin's late-2026 launch increasingly credible:

1. SK Hynix HBM4 ramp

SK Hynix began sampling 12-Hi HBM4 stacks in Q2 2026 and is on track for mass production in Q3 2026. Nvidia is SK Hynix's anchor HBM4 customer (per Reuters reporting, July 2026). Samsung and Micron are also qualifying HBM4 but lagging ~6 months behind SK Hynix.

2. TSMC CoWoS-L capacity

TSMC's CoWoS-L line (used for Rubin + Rubin Ultra) reached 35,000 wafer-starts/month in August 2026, up from 12,000 in early 2026. This expansion is specifically for Nvidia + AMD MI400 demand. Bloomberg reports TSMC is allocating ~60% of CoWoS-L capacity to Nvidia and ~25% to AMD through 2027.

3. Foxconn + Inventec server rack assembly

Foxconn has been running Rubin reference platform builds (NVL72 rack scale) since May 2026. Inventec is the secondary ODM. Both are scaling for 4Q26 hyperscaler deployments.

Why Rubin matters for inference

The shift to inference-first design reflects a hard economic reality: training compute is doubling every 6 months but inference compute (tokens served per user) is doubling every 3 months as model deployment scales. By 2027, hyperscalers like Microsoft and Google expect 70%+ of AI-related GPU spend to go to inference rather than training.

Rubin's higher FP4/INT8 throughput per watt vs Blackwell directly addresses this. Microsoft's Maia 2 and Google's TPU v7 (covered in our hyperscaler custom-silicon piece) are also inference-first, suggesting the industry has converged on this design point.

What is Rubin Ultra?

Rubin Ultra is the chiplet-based follow-up to Rubin, scheduled for H2 2027. It uses two Rubin dies on a single CoWoS-L interposer, quadrupling memory capacity (1TB HBM4e) and FP4 throughput (~100,000 TOPS). Rubin Ultra is the first Nvidia GPU designed explicitly for million-token-context inference workloads.

Rubin Ultra is also the first Nvidia GPU to use optical interconnects (via NVLink Switch 6) for chip-to-chip communication beyond the local socket. This is a significant architectural shift that competitors (AMD MI450, TPU v8) are also pursuing.

What to watch

Four signals over the next 6 months will confirm or refute the current Rubin timeline:

1. Nvidia GTC 2027 (March 2027) — expect Rubin Ultra + Rubin Ultra rack-scale (NVL576) disclosures.
2. Hyperscaler earnings — Microsoft, Google, Meta capex guidance for 2027 will indicate Rubin + Rubin Ultra order volumes.
3. TSMC Q4 2026 earnings — CoWoS-L utilization rate will show whether Nvidia is pulling capacity forward.
4. AMD MI400 launch (Q1 2027) — competitive pressure may force Nvidia to bring Rubin Ultra forward by a quarter.

For buyers, Rubin's launch is unlikely to affect consumer GPU pricing — the data-center Rubin line is sold separately from GeForce. But Rubin's success does determine how aggressively AMD, Intel, and the hyperscaler in-house silicon programs compete in 2027-2028, which ultimately affects consumer AI features in phones and laptops.

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Bottom line: Nvidia Rubin is on track for Q4 2026 launch with HBM4 memory, TSMC 3nm, and inference-first design. Supply-chain signals from SK Hynix, TSMC, and Foxconn all corroborate the timeline. Rubin Ultra follows in H2 2027 with chiplet architecture and optical interconnects. The competitive question is whether AMD MI400 (early 2027) and hyperscaler in-house silicon (TPU v7, Maia 2, Trainium 3) can peel off enough inference workloads to slow Nvidia's data-center share gains.